1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Flash memories have become widespread as semiconductor devices having nonvolatile memory functions. A flash memory includes a floating gate between a gate electrode and a channel formation region of a transistor included in a memory element and stores data by holding charge in the floating gate (e.g., Patent Document 1).
In a flash memory, the multi-level technique by which plural bits of data can be stored in one memory cell has been in practical use (e.g., Patent Document 2). By the multi-level technique, the area of the memory cell per bit can be reduced.
However, in a flash memory, a gate insulating layer between a floating gate and a channel formation region of a transistor included in a memory element deteriorates because of tunneling current generated in writing. This results in a problem in that the data retention characteristics of the memory element are degraded after a predetermined number of writing operations. To reduce adverse effects of this problem, a method in which the number of writing operations of memory elements is equalized is employed, for example. However, a complicated peripheral circuit is needed to employ this method. Moreover, even when such a method is employed, the fundamental problem of lifetime cannot be resolved. In other words, a flash memory is not suitable for applications in which data is frequently rewritten.
In addition, in the flash memory, a high voltage is necessary for holding of charge in the floating gate or removal of the charge and a step-up circuit for generating a high voltage is also necessary.